STM32F103 RTC регистры настройки часов

Часы (RTC) представляют собой независимый таймер, который с помощью соответствующего программного обеспечения может выполнять функции часов и календаря. Питание может осуществлятся от отдельного источника Vbat от которого кроме регистров часов питается и так называемый Backup Domain (или батарейный домен). В него входят, кроме регистров RTC, LSE генератор и выводы с PC13 до PC15, обеспечивающие функционирование часов реального времени даже при отключенном питании на Vdd.  Для установки текущего значения счетчика (времени и даты) необходимо: 

• включить тактирование интерфейса доступа к регистрам часов и Backup domain PWREN BKPEN выполнив команду 

          RCC->APB1ENR |= RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN;

• установить бит  DBP регистра PWR_CR, разрешающий доступ к  Backup domain

         PWR->CR |= PWR_CR_DBP;

RTC control register high (RTC_CRH)
Address offset: 0x00
Reset value: 0x0000

Bits 15:3 Reserved, forced by hardware to 0.

Bit 2 OWIE: Overflow interrupt enable

0: Overflow interrupt is masked.

1: Overflow interrupt is enabled.

Bit 1 ALRIE: Alarm interrupt enable

0: Alarm interrupt is masked.

1: Alarm interrupt is enabled.

Bit 0 SECIE: Second interrupt enable

0: Second interrupt is masked.

1: Second interrupt is enabled.

These bits are used to mask interrupt requests. Note that at reset all interrupts are disabled, so it is possible to write to the RTC registers to ensure that no interrupt requests are pending after initialization. It is not possible to write to the RTC_CRH register when the peripheral is completing a previous write operation (flagged by RTOFF=0, see Section 18.3.4 on page 466).

The RTC functions are controlled by this control register. Some bits must be written using a specific configuration procedure (see Configuration procedure:).

RTC control register low (RTC_CRL)
Address offset: 0x04
Reset value: 0x0020

Bits 15:6 Reserved, forced by hardware to 0.
Bit 5 RTOFF: RTC operation OFF
With this bit the RTC reports the status of the last write operation performed on its registers, indicating if it has been completed or not. If its value is ‘0’ then it is not possible to write to any of the RTC registers. This bit is read only.
0: Last write operation on RTC registers is still ongoing.
1: Last write operation on RTC registers terminated.
Bit 4 CNF: Configuration flag
This bit must be set by software to enter in configuration mode so as to allow new values to be written in the RTC_CNT, RTC_ALR or RTC_PRL registers. The write operation is only executed when the CNF bit is reset by software after has been set.
0: Exit configuration mode (start update of RTC registers).
1: Enter configuration mode.
Bit 3 RSF: Registers synchronized flag
This bit is set by hardware at each time the RTC_CNT and RTC_DIV registers are updated and cleared by software. Before any read operation after an APB1 reset or an APB1 clock stop, this bit must be cleared by software, and the user application must wait until it is set to be sure that the RTC_CNT, RTC_ALR or RTC_PRL registers are synchronized.
0: Registers not yet synchronized.
1: Registers synchronized.
Bit 2 OWF: Overflow flag
This bit is set by hardware when the 32-bit programmable counter overflows. An interrupt is generated if OWIE=1 in the RTC_CRH register. It can be cleared only by software. Writing ‘1’ has no effect.
0: Overflow not detected
1: 32-bit programmable counter overflow occurred.
Bit 1 ALRF: Alarm flag
This bit is set by hardware when the 32-bit programmable counter reaches the threshold set in the RTC_ALR register. An interrupt is generated if ALRIE=1 in the RTC_CRH register. It can be cleared only by software. Writing ‘1’ has no effect.
0: Alarm not detected
1: Alarm detected
Bit 0 SECF: Second flag
This bit is set by hardware when the 32-bit programmable prescaler overflows, thus incrementing the RTC counter. Hence this flag provides a periodic signal with a period corresponding to the resolution programmed for the RTC counter (usually one second). An interrupt is generated if SECIE=1 in the RTC_CRH register. It can be cleared only by software. Writing ‘1’ has no effect.
0: Second flag condition not met.
1: Second flag condition met.

The functions of the RTC are controlled by this control register. It is not possible to write to the RTC_CR register while the peripheral is completing a previous write operation (flagged by RTOFF=0, see Section 18.3.4 on page 466).
Note:
1 Any flag remains pending until the appropriate RTC_CR request bit is reset by software, indicating that the interrupt request has been granted.
2 At reset the interrupts are disabled, no interrupt requests are pending and it is possible to write to the RTC registers.
3 The OWF, ALRF, SECF and RSF bits are not updated when the APB1 clock is not running.
4 The OWF, ALRF, SECF and RSF bits can only be set by hardware and only cleared by software.
5 If ALRF = 1 and ALRIE = 1, the RTC global interrupt is enabled. If EXTI Line 17 is also enabled through the EXTI Controller, both the RTC global interrupt and the RTC Alarm interrupt are enabled.
6 If ALRF = 1, the RTC Alarm interrupt is enabled if EXTI Line 17 is enabled through the EXTI Controller in interrupt mode. When the EXTI Line 17 is enabled in event mode, a pulse is generated on this line (no RTC Alarm interrupt generation).

RTC prescaler load register (RTC_PRLH / RTC_PRLL)
The Prescaler Load registers keep the period counting value of the RTC prescaler. They are write-protected by the RTOFF bit in the RTC_CR register, and a write operation is allowed if the RTOFF value is ‘1’.

RTC prescaler load register high (RTC_PRLH)
Address offset: 0x08
Write only (see Section 18.3.4 on page 466)

Reset value: 0x0000

Bits 15:4 Reserved, forced by hardware to 0.
Bits 3:0 PRL[19:16]: RTC prescaler reload value high
These bits are used to define the counter clock frequency according to the following formula:
f_TR_CLK = f_RTCCLK/(PRL[19:0]+1)

RTC prescaler load register low (RTC_PRLL)
Address offset: 0x0C
Write only (see Section 18.3.4 on page 466)

Reset value: 0x8000

Bits 15:0 PRL[15:0]: RTC prescaler reload value low
These bits are used to define the counter clock frequency according to the following formula:
fTR_CLK = fRTCCLK/(PRL[19:0]+1)
Caution: The zero value is not recommended. RTC interrupts and flags cannot be
asserted correctly.

Note: If the input clock frequency (fRTCCLK) is 32.768 kHz, write 7FFFh in this register to get a
signal period of 1 second.

RTC prescaler divider register (RTC_DIVH / RTC_DIVL)
During each period of TR_CLK, the counter inside the RTC prescaler is reloaded with the
value stored in the RTC_PRL register. To get an accurate time measurement it is possible to
read the current value of the prescaler counter, stored in the RTC_DIV register, without
stopping it. This register is read-only and it is reloaded by hardware after any change in the

RTC_PRL or RTC_CNT registers.

RTC prescaler divider register high (RTC_DIVH)
Address offset: 0x10

Reset value: 0x0000

Bits 15:4 Reserved
Bits 3:0 RTC_DIV[19:16]: RTC clock divider high

RTC prescaler divider register low (RTC_DIVL)
Address offset: 0x14
Reset value: 0x8000

Bits 15:0 RTC_DIV[15:0]: RTC clock divider low

RTC counter register (RTC_CNTH / RTC_CNTL)

The RTC core has one 32-bit programmable counter, accessed through two 16-bit registers;
the count rate is based on the TR_CLK time reference, generated by the prescaler.
RTC_CNT registers keep the counting value of this counter. They are write-protected by bit
RTOFF in the RTC_CR register, and a write operation is allowed if the RTOFF value is ‘1’. A
write operation on the upper (RTC_CNTH) or lower (RTC_CNTL) registers directly loads the
corresponding programmable counter and reloads the RTC Prescaler. When reading, the
current value in the counter (system date) is returned.

RTC counter register high (RTC_CNTH)
Address offset: 0x18
Reset value: 0x0000

Bits 15:0 RTC_CNT[31:16]: RTC counter high
Reading the RTC_CNTH register, the current value of the high part of the RTC Counter
register is returned. To write to this register it is necessary to enter configuration mode (see
Section 18.3.4: Configuring RTC registers on page 466).

RTC counter register low (RTC_CNTL)
Address offset: 0x1C

Reset value: 0x0000

Bits 15:0 RTC_CNT[15:0]: RTC counter low
Reading the RTC_CNTL register, the current value of the lower part of the RTC Counter
register is returned. To write to this register it is necessary to enter configuration mode (see
Section 18.3.4: Configuring RTC registers on page 466).

RTC alarm register high (RTC_ALRH / RTC_ALRL)
When the programmable counter reaches the 32-bit value stored in the RTC_ALR register,
an alarm is triggered and the RTC_alarmIT interrupt request is generated. This register is
write-protected by the RTOFF bit in the RTC_CR register, and a write operation is allowed if

the RTOFF value is ‘1’.

RTC alarm register high (RTC_ALRH)
Address offset: 0x20
Write only (see Section 18.3.4 on page 466)
Reset value: 0xFFFF

Bits 15:0 RTC_ALR[31:16]: RTC alarm high
The high part of the alarm time is written by software in this register. To write to this register
it is necessary to enter configuration mode (see Section 18.3.4: Configuring RTC registers
on page 466).

RTC alarm register low (RTC_ALRL)
Address offset: 0x24
Write only (see Section 18.3.4 on page 466)

Reset value: 0xFFFF

Bits 15:0 RTC_ALR[15:0]: RTC alarm low
The low part of the alarm time is written by software in this register. To write to this register it
is necessary to enter configuration mode (see Section 18.3.4: Configuring RTC registers on
page 466).

RTC register map

Backup domain control register (RCC_BDCR)
Address offset: 0x20
Reset value: 0x0000 0000, reset by Backup domain Reset.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
Сброс (установка в 0) происходит с помощью процедуры Backup domain Reset.

   Note: The LSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register (RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are writeprotected and the DBP bit in the Power control register (PWR_CR) has to be set before these can be modified.  These bits are only reset after a Backup domain Reset. Any internal or external Reset will not have any effect on these bits.
   Биты LSEON, LSEBYP, RTCSEL и RTCEN регистра RCC_BDCR входят в Backup domain - регистры, питающиеся от независимого источника питания (батарейки). После процедуры сброса (Reset) эти биты защищены от записи и для их модификации необходимо установить бит DBP в Power control register (PWR_CR). Любая внешняя или внутренняя процедура сброса не влияет на данные биты.

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 BDRST: Backup domain software reset
Set and cleared by software.
0: Reset not activated
1: Resets the entire Backup domain

Bit 15 RTCEN: RTC clock enable
Set and cleared by software.
0: RTC clock disabled
1: RTC clock enabled

Bits 14:10 Reserved, must be kept at reset value.

Bits 9:8 RTCSEL[1:0]: RTC clock source selection
Set by software to select the clock source for the RTC. Once the RTC clock source has been
selected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit
can be used to reset them.
00: No clock
01: LSE oscillator clock used as RTC clock10: LSI oscillator clock used as RTC clock
11: HSE oscillator clock divided by 128 used as RTC clock

Bits 7:3 Reserved, must be kept at reset value.

Bit 2 LSEBYP: External low-speed oscillator bypass
Set and cleared by software to bypass oscillator in debug mode. This bit can be written only
when the external 32 kHz oscillator is disabled.
0: LSE oscillator not bypassed
1: LSE oscillator bypassed

Bit 1 LSERDY: External low-speed oscillator ready

Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After
the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock
cycles.
0: External 32 kHz oscillator not ready
1: External 32 kHz oscillator ready

Bit 0 LSEON: External low-speed oscillator enable
Set and cleared by software.
0: External 32 kHz oscillator OFF
1: External 32 kHz oscillator ON