ADS 1246/7/8 предназначены для измерения температуры с помощь терморезисторов (RTD resistive temperature device) или термопар (thermocouple). Высокая точность измерений достигается благодаря использованию 24-разрядного АЦП, интегрированного входного мультиплексора и ЦАП, задающего измерительный ток.
MUX0—Multiplexer Control Register 0. This register allows any combination of differential inputs to be selected on any of the input channels.
Bits 7:6 BCS1:0
These bits select the magnitude of the sensor detect current source.(Ток сенсора для определения обрыва входной цепи).
00 = Burnout current source off (default)
01 = Burnout current source on, 0.5μA
10 = Burnout current source on, 2μA
11 = Burnout current source on, 10μA
Bits 5:3 MUX_SP2:0
Positive input channel selection bits. (Выбор входного канала для положительного входа)
000 = AIN0 (default)
001 = AIN1
010 = AIN2
011 = AIN3
100 = AIN4 (ADS1248 only)
101 = AIN5 (ADS1248 only)
110 = AIN6 (ADS1248 only)
111 = AIN7 (ADS1248 only)
Bits 2:0 MUX_SN2:0
Negative input channel selection bits. (Выбор входного канала для отрицательного входа)
000 = AIN0
001 = AIN1 (default)
010 = AIN2
011 = AIN3
100 = AIN4 (ADS1248 only)
101 = AIN5 (ADS1248 only)
110 = AIN6 (ADS1248 only)
111 = AIN7 (ADS1248 only)
VBIAS—Bias Voltage Register
Bits 7:0 VBIAS7:0
These bits apply a bias voltage of midsupply (AVDD + AVSS)/2 to the selected analog input. (Подключает к соответствующим входам напряжение смещения, равное половине напряжения питания).
0 = Bias voltage not enabled (default)
1 = Bias voltage is applied on the corresponding analog input (bit 0 corresponds to AIN0, etc.).
MUX1—Multiplexer Control Register 1
Bit 7 CLKSTAT
This bit is read-only and indicates whether the internal or external oscillator is being used.
0 = Internal oscillator in use
1 = External oscillator in use
Bits 6:5 VREFCON1:0
These bits control the internal voltage reference. These bits allow the reference to be turned on or
off completely, or allow the reference state to follow the state of the device. Note that the internal
reference is required for operation of the IDAC functions.
00 = Internal reference is always off (default)
01 = Internal reference is always on
10 or 11 = Internal reference is on when a conversion is in progress and shuts down when the
device receives a shutdown opcode or the START pin is taken low
Bits 4:3 REFSELT1:0
These bits select the reference input for the ADC.
00 = REF0 input pair selected (default)
01 = REF1 input pair selected (ADS1248 only)
10 = Onboard reference selected
11 = Onboard reference selected and internally connected to pin REFP0, REFPN0
Bits 2:0 MUXCAL2:0
These bits are used to select a system monitor. The MUXCAL selection supercedes selections
from registers MUX0 and MUX1 (MUX_SP, MUX_SN, and VBIAS).
000 = Normal operation (default)
001 = Offset measurement
010 = Gain measurement
011 = Temperature diode
100 = External REF1 measurement (ADS1248 only)
101 = External REF0 measurement
110 = AVDD measurement
111 = DVDD measurement
Table 21 provides the ADC input connection and PGA settings for each MUXCAL setting. The PGA setting reverts to the original SYS0 register setting when MUXCAL is taken back to normal operation or offset measurement.
SYS0—System Control Register 0
Bit 7 This bit must always be set to '0'
Bits 6:4 PGA2:0
These bits determine the gain of the PGA.
000 = 1 (default)
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = 64
111 = 128
Bits 3:0 DOR3:0
These bits select the output data rate of the ADC. Bits with a value higher than 1001 select the
highest data rate of 2000SPS.
0000 = 5SPS (default)
0001 = 10SPS
0010 = 20SPS
0011 = 40SPS
0100 = 80SPS
0101 = 160SPS
0110 = 320SPS
0111 = 640SPS
1000 = 1000SPS
1001 to 1111 = 2000SPS
OFC23:0
These bits make up the offset calibration coefficient register of the ADS1248.
FSC23:0
These bits make up the full-scale calibration coefficient register.
IDAC0—IDAC Control Register 0
Bits 7:4 ID3:0
Read-only, factory-programmed bits; used for revision identification.
Bit 3 DRDY MODE
This bit sets the DOUT/DRDY pin functionality. In either setting of the DRDY MODE bit, the DRDY pin continues to indicate data ready, active low.
0 = DOUT/DRDY pin functions only as Data Out (default)
1 = DOUT/DRDY pin functions both as Data Out and Data Ready, active low
Bits 2:0 IMAG2:0
The ADS1247/8 have two programmable current source DACs that can be used for sensor
excitation. The IMAG bits control the magnitude of the excitation current. The IDACs require the
internal reference to be on.
000 = off (default)
001 = 50μA
010 = 100μA
011 = 250μA
100 = 500μA
101 = 750μA
110 = 1000μA
111 = 1500μA
IDAC1—IDAC Control Register 1
The two IDACs on the ADS1247/8 can be routed to either the IEXC1 and IEXC2 output pins or directly to the analog inputs.
Bits 7:4 I1DIR3:0
These bits select the output pin for the first current source DAC.
0000 = AIN0
0001 = AIN1
0010 = AIN2
0011 = AIN3
0100 = AIN4 (ADS1248 only)
0101 = AIN5 (ADS1248 only)
0110 = AIN6 (ADS1248 only)
0111 = AIN7 (ADS1248 only)
10x0 = IEXT1 (ADS1248 only)
10x1 = IEXT2 (ADS1248 only)
11xx = Disconnected (default)
Bits 3:0 I2DIR3:0
These bits select the output pin for the second current source DAC.
0000 = AIN0
0001 = AIN1
0010 = AIN2
0011 = AIN3
0100 = AIN4 (ADS1248 only)
0101 = AIN5 (ADS1248 only)
0110 = AIN6 (ADS1248 only)
0111 = AIN7 (ADS1248 only)
10x0 = IEXT1 (ADS1248 only)
10x1 = IEXT2 (ADS1248 only)
11xx = Disconnected (default)
Default setup of registers:
MUX0 = 0x00
VBIAS = 0x00 No Bias Voltage enabled
MUX1 = 0x00
SYS0 = 0x00 PGA = 1, Data Rate = 5SPS
OFC0 = 0x00
OFC1 = 0x00
OFC2 = 0x00
FSC0 = 0x00
FSC1 = 0x00
FSC2 = 0x00
IDAC0 = 0x00
IDAC1 = 0xFF
GPIOCFG = 0x00
GPIODIR = 0x00
GPIODAT = 0x00
SYSTEM CONTROL COMMANDS
WAKEUP 0000 000x (00h, 01h)
-Wake up from sleep mode that is set by the SLEEP command. Use this command to awaken the device from sleep mode. After execution of the WAKEUP command, the device wakes up on the rising edge of the eighth SCLK.
Используется для выхода устройства из режима SLEEP, После подачи команды WAKEUP АЦП включается по заднему фронту 8-го импульса SCLK.
SLEEP 0000 001x (02h, 03h)
-Set the device to sleep mode; can only be awakened by the WAKEUP command. This command places the part into a sleep (power-saving) mode. When the SLEEP command is issued, the device completes the current conversion and then goes into sleep mode. Note that this command does not automatically power-down the internal voltage reference; see the VREFCON bits in the MUX1 register for each device for further details. To exit sleep mode, issue the WAKEUP command. Single conversions can be performed by issuing a WAKEUP command followed by a SLEEP command. Both WAKEUP and SLEEP are the software command equivalents of using the START pin to control the device.
Подача команды приводит к переходу в режим сна, из которого его можно вывести только командой WAKEUP. При подаче SLEEP, устройство завершает текущее преобразование и переходит в режим сна. Однократное преобразование преобразование можно запустить подачей команды WAKEUP. Обе команды WAKEUP & SLEEP эквивалентны использованию вывода START. Если вывод START удерживается на низком уровне, то команда WAKEUP не выводит устройство из режима сна. Вывод CS должен удерживаться на низком уровне в режиме сна.
SYNC 0000 010x (04h, 05h)
-Synchronize DRDY.
This command resets the ADC digital filter and starts a new conversion. The DRDY pin from multiple devices connected to the same SPI bus can be synchronized by issuing a SYNC command to all of devices simultaneously.
Синхронизация АЦП преобразования. Подача команды сбрасывает фильтр АЦП и запускает новое преобразование. Вывод DRDY, подключенный к SPI от нескольких устройств можно синхронизировать, подавая команду SYNC одновременно на все устройства.
RESET 0000 011x (06h, 07h)
-Reset the device to power-up state.
This command restores the registers to the respective power-up values. This command also resets the digital filter. RESET is the command equivalent of using the RESET pin to reset the device. However, the RESET command does not reset the SPI interface. If the RESET command is issued when the SPI interface is in the wrong state, the device does not reset. The CS pin can be used to reset SPI interface first, and then a RESET command can be issued to reset the device. The RESET command holds the registers and the decimation filter in a reset state for 0.6ms when the system clock frequency is 4.096MHz, similar to the hardware reset. Therefore, SPI communication can be only be started 0.6ms after the RESET command is issued, as shown in Figure 75.
DATA RETRIEVAL COMMANDS
RDATAC 0001 010x (14h, 15h)
-Read data continuously.
The RDATAC command enables the automatic loading of a new conversion result into the output data register. In this mode, the conversion result can be received once from the device after the DRDY signal goes low by sending 24 SCLKs. It is not necessary to read back all the bits, as long as the number of bits read out is a multiple of eight. The RDATAC command must be issued after DRDY goes low, and the command takes effect on the next DRDY. Be sure to complete data retrieval (conversion result or register read-back) before DRDY goes low, or the resulting data will be corrupt. Successful register read operations in RDATAC mode require the knowledge of when the next DRDY falling edge occurs.
When the START pin is held low, the device is in sleep mode. In Sleep mode the only the RDATA, RDATAC, SDATAC, WAKEUP and NOP commands can be issued. Another thing to remember is that the RESET pin must be held high. In order to implement WREG and RREG the START pin must held high. You could set the START pin low after configuring the device...
Существуют различные методы чтения результатов измерений из АЦП:
- Когда АЦП включен и на вывод START=1, то АЦП выдает данные с запрограммированной скоростью. По умолчанию АЦП находится в режиме (mode) RDATAC (Read Data Continuously) - непрерывное чтение данных). Данные могут быть получены при посылке 24 SCLK's после того как установится низкий уровень DRDY (=0). Команду RDATAC (0001 010Х - т.е. 0х14 или 0х15) можно подать после установки низкого уровня DRDY (=0). Команда начнет выполнятся с приходом следующего низкого уровня DRDY (=0). Таким образом, для корректного чтения результатов необходимо ожидать спадающий фронт DRDY.
SDATAC 0001 011x (16h, 17h)
-Stop reading data continuously.
The SDATAC command terminates the RDATAC mode. Afterwards, the conversion result is not automatically loaded into the output shift register when DRDY goes low, and register read operations can be performed without interruption from new conversion results being loaded into the output shift register. Use the RDATA command to retrieve conversion data. The SDATAC command takes effect after the next DRDY.
RDATA 0001 001x (12h, 13h)
-Read data once.
The RDATA command loads the most recent conversion result into the output register. After issuing this command, the conversion result can be read out by sending 24 SCLKs, as shown in Figure 78. This command also works in RDATAC mode. When performing multiple reads of the conversion result, the RDATA command can be sent when the last eight bits of the conversion result are being shifted out during the course of the first read operation by taking advantage of the duplex communication nature of the SPI interface, as shown in Figure 79.
USER REGISTER READ AND WRITE COMMANDS
RREG—Read from registers.
This command outputs the data from up to 16 registers, starting with the register address specified as part of the instruction. The number of registers read is one plus the second byte. If the count exceeds the remaining registers, the addresses wrap back to the beginning. First Command Byte: 0010 rrrr, where rrrr is the address of the first register to read. Second Command Byte: 0000 nnnn, where nnnn is the number of bytes to read –1. It is not possible to use the full-duplex nature of the SPI interface when reading out the register data. For example, a SYNC command cannot be issued when reading out the VBIAS and MUX1 data, as shown in Figure 80. Any command sent during the readout of the register data is ignored. Thus, it is advisable to send NOP through the DIN when reading out the register data.
This command writes to the registers, starting with the register specified as part of the instruction. The number of registers that are written is one plus the value of the second byte. First Command Byte: 0100 rrrr, where rrrr is the address of the first register to be written. Second Command Byte: 0000 nnnn, where nnnn is the number of bytes to be written – 1. Data Byte(s): data to be written to the registers.
CALIBRATION COMMANDS
The ADS1246/7/8 provide system and offset calibration commands and a system gain calibration command.
SYSOCAL—Offset system calibration.
This command initiates a system offset calibration. For a system offset calibration, the input should be externally set to zero. The OFC register is updated when this operation completes.
SYSGCAL—System gain calibration.
This command initiates the system gain calibration. For a system gain calibration, the input should be set to full-scale. The FSC register is updated after this operation.
SELFOCAL—Self offset calibration.
This command initiates a self-calibration for offset. The device internally shorts the inputs and performs the calibration. The OFC register is updated after this operation.
Если необходимо записать данные в регистры конфигурации необходимо установить вывод START в высокое состояние (START =1), и послать команду WREG с необходимым количеством байт для записи.
Для чтения содержимого регистров посылается команда RREG.
Для безошибочного выполнения данных команд необходимо сначала подать команду SDATAC (0001 011Х - т.е. 0х16 или 0х17).
Метод проверки связи с АЦП:
1) Установить START high (=1) и RESET high (=1)
2) Послать команду SDATAC (x16h)
3) Послать команду WREG x420030h. Запись в регистр MUX1 (в данном случае для примера включают Internal Reference и используют его для получения результатов).
4) Послать команду RREG x2200XXh. Чтение регистра MUX1. Мы должны получить в ответ х30.
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