RFM95/96/97/98(W) - Low Power Long Range Transceiver Module V1.0

FSK, GFSK, MSK, GMSK, LoRaTM and OOK modulation

The SPI interface gives access to the configuration register via a synchronous full-duplex protocol corresponding to
CPOL = 0 and CPHA = 0 in Motorola/Freescale nomenclature. Only the slave side is implemented.
Three access modes to the registers are provided:
􀂊 SINGLE access: an address byte followed by a data byte is sent for a write access whereas an address byte is sent and
a read byte is received for the read access. The NSS pin goes low at the beginning of the frame and goes high after the
data byte.
􀂊 BURST access: the address byte is followed by several data bytes. The address is automatically incremented internally
between each data byte. This mode is available for both read and write accesses. The NSS pin goes low at the
beginning of the frame and stay low between each byte. It goes high only after the last byte transfer.
􀂊 FIFO access: if the address byte corresponds to the address of the FIFO, then succeeding data byte will address the
FIFO. The address is not automatically incremented but is memorized and does not need to be sent between each data
byte. The NSS pin goes low at the beginning of the frame and stay low between each byte. It goes high only after the
last byte transfer.

SPI Timing Diagram (single access)

MOSI is generated by the master on the falling edge of SCK and is sampled by the slave (i.e. this SPI interface) on the

rising edge of SCK. MISO is generated by the slave on the falling edge of SCK.

A transfer is always started by the NSS pin going low. MISO is high impedance when NSS is high.

The first byte is the address byte. It is comprises:

􀂊 A wnr bit, which is 1 for write access and 0 for read access.

􀂊 Then 7 bits of address, MSB first.

The second byte is a data byte, either sent on MOSI by the master in case of a write access or received by the master on

MISO in case of read access. The data byte is transmitted MSB first.

Proceeding bytes may be sent on MOSI (for write access) or received on MISO (for read access) without a rising NSS

edge and re-sending the address. In FIFO mode, if the address was the FIFO address then the bytes will be written / read

at the FIFO address. In Burst mode, if the address was not the FIFO address, then it is automatically incremented for each

new byte received.

The frame ends when NSS goes high. The next frame must start with an address byte. The SINGLE access mode is

therefore a special case of FIFO / BURST mode with only 1 data byte transferred.

During the write access, the byte transferred from the slave to the master on the MISO line is the value of the written

register before the write operation.

Six of RFM95/96/97/98(W)’s general purpose IO pins are available used in LoRaTM mode. Their mapping is shown

below and depends upon the configuration of registers RegDioMapping1 and RegDioMapping2.